1. Technical Field of the Invention
The present invention generally relates to clock distribution techniques in telecommunications equipment. More particularly, and not by way of any limitation, the present invention is directed to a system and method of compensating for timing source transients in connection with DS0 telecommunications links.
2. Description of Related Art
For error-free transmission of DS0 data between two telecommunications devices located at a site, industry standards require that the data transmission circuitry of each device use a raw, unfiltered, 64 KHz composite clock signal from a building integrated timing source (“BITS”) to define the data bit edges. Since each DS0 device uses this clock to recover data received from other DS0 devices, each DS0 device's transmit data must be appropriately aligned to the composite clock's 8 KHz frame. Furthermore, the device's central clock must not filter the composite clock wander and transients, but must follow them so that clock-to-data skew is minimized at the devices. On the other hand, if this same unfiltered clock signal is used to transmit data to or operate non-DS0 circuitry within other devices, the erratic nature of the composite clock can cause timing hazards and corrupt data in those circuits.
It is possible that a single system will include circuitry having different timing requirements. For example, a signaling server such as that described in the above-noted U.S. patent application Ser. No. 09/541,002, entitled “CLOCK DISTRIBUTION SCHEME IN A SIGNALING SERVER”, may accommodate both phase-dependent (e.g., DS0) links as well as non-phase-dependent (e.g., DS1, T-1, SONET) links. This can be accomplished by providing within the system two separate timing distribution mechanisms, one for the phase-dependent links and an other for the non-phase-dependent links. Such duplication clearly adds complexity both to cabling and circuitry requirements of the system, as well as increasing the associated software overhead involved in configuring and monitoring the timing distribution mechanism. Moreover, increasingly stringent space-limitations on system packaging standards require that the number of signals and cables in a system be minimized.
An alternative means for enabling the timing requirements of both phase-dependent and non-phase-dependent links in the same system to be accommodated is disclosed in the above-noted related U.S. Patent Application, entitled METHOD AND SYSTEM FOR EMBEDDING A FIRST CLOCK SIGNAL PHASE WITHIN A SECOND SIGNAL, which has been incorporated by reference in its entirety. The combination of the techniques described in the referenced patent application results in the ability to implement a single generic timing distribution system in a telecommunications node that includes both phase-dependent and non-phase-dependent links.
It will be recognized that upper tier system disturbances may cause such a generic timing distribution system implemented in a telecommunications system to be forced to switch from one timing reference signal to a second timing reference signal. When such a timing switchover occurs, a temporary misalignment between the distributed DS0 data and the associated frame reference signals may occur. If such a misalignment is propagated from the timing distribution system to the DS0 link function, then transmission and reception of DS0 frames will be corrupted.
During normal operation, the generic timing distribution system referred to herein provides a 8.192 MHz clock, a 19.44 MHz clock, and a framed reference signal comprising a Super Frame Indicator (“SFI”) signal to a plurality of line cards, including, for example, a DS0 interface module (“DIM”) card. The SFI signal is transmitted using the 19.44 MHz clock. The 8.192 MHz clock and the 19.44 MHz clocks are aligned on 125 μs boundaries and are synchronized to an external timing reference from a Building Integrated Timing Source (“BITS”). As described in the above-noted U.S. patent application Ser. No. 09/541,002, entitled “CLOCK DISTRIBUTION SCHEME IN A SIGNALING SERVER”, the SFI carries control information, including a link frame position indication, to downstream cards.
In particular, the SFI signal is a serially encoded framed control signal comprising a plurality of fields for controlling the proper distribution of clock signals and for transmitting commands to system modules. Accordingly, the SFI signal comprises timing and control information addressed to individual modules of a system. In one embodiment, the SFI signal comprises timeslots, each of which is assigned to a module. Each timeslot has a header, which may comprise a six-bit synchronization word. In order to provide synchronization, bits of the timeslot excluding the header may be repeated twice, so a module receiving the signal may synchronize itself by evaluating the synchronization word of the SFI signal. The SFI signal may include a phase of a timing signal, for example, a composite clock signal.
The SFI signal may include a signal selection command that instructs each module to select a specific derived clock signal from the signals received from the downstream modules and to send the selected derived clock signal upstream.
As previously noted, under certain conditions, the timing distribution system may determine that the external reference is no longer viable and a switchover to a new external reference will occur. During the switchover, the alignment between the 8.192 MHz and the 19.44 MHz clocks may be temporarily skewed. In order to continue the uninterrupted transmission and reception of DS0 traffic, the DS0 function must be able to compensate for this input reference skewing. Because this problem arises from the use of a single timing distribution mechanism for both DS0 and other links, the prior art suggests no solution to this problem.